The present invention relates to a full adder circuit, and more specifically to a full adder circuit for transmitting a carry signal differentially from a less significant bit full adder to a more significant bit full adder.
FIG. 1 shows an adder circuit related to the present invention, in which two carry signals are inputted from a preceding stage full adder as complementary differential carry signals; addition data is obtained on the basis of the carry signals and data to be added; and the other carry signals are transmitted to a succeeding stage full adder.
In more detail, the complementary carry signals Cin and /Cin are inputted from the preceding stage full adder to the present full adder. In this full adder, when the signal level of the carry signal Cin is higher than that of the carry signal /Cin, a carry is not generated to the succeeding stage bit. In contrast with this, when the signal level of the carry signal Cin is lower than that of the carry signal /Cin, a carry is generated to the succeeding stage bit. Between two input terminals for inputting the carry signals C and /C from the preceding stage bit and two output terminals for outputting the carry signals Cout and /Cout to the succeeding stage bit, two signal lines 131 and 133 are connected to transmit the carry signals, respectively. Between the two signal lines 131 and 133, two N-channel transistors 127 and 129 are provided as transfer gates of the signal lines.
Before operation, a precharge signal PREC is inputted to the gates of two N-channel transistors 137 and 139 to turn on these transistors, so that the signal lines 131 and 133 are precharged to a predetermined level. Further, the two signal lines 131 and 133 are equalized to the same potential through an N-channel transistor 142 also turned on in response to the precharge signal PREC. In the same way as above, the precharge signal PREC is inputted to the gate of an N-channel transistor 135 to turn on this transistor, so that the two input terminal for inputting the carry signals Cin and /Cin are equalized to the same potential through this N-channel transistor 135. After that, the transistors 137 and 139 are both turned off to execute the addition operation.
In the present stage bit, two data A and B are added. When both data are at the logical [1] level, a carry must be generated to the succeeding stage bit, irrespective of the carry signals Cin and /Cin applied by the lower significant bit. In this case, an EX-OR circuit 116 (to which two input data A and B are applied) outputs a logical [0] level signal to the gates of the N-channel transistors 127 and 129, so that these transistors are both turned off. As a result, the carry signals Cin and /Cin are both not transmitted to the succeeding stage bit.
The EX-OR circuit 116 and a NAND circuit 117 (to both of which the input data A and B are applied) output both a logical [0] level signal, respectively. These two logical [0] level signal of the circuits 116 and 117 and the logical [0] level signal of the precharge signal PREC are all inputted to a NAND circuit 120, so that the NAND circuit 120 outputs the logical [1] level signal. This signal is given to the gate of an N-channel transistor 123 to turn it on, with the result that the signal line 131 is discharged to a low potential Vss. In contrast with this, a NAND circuit 121 outputs a logical [0] level signal. This signal is given to the gate of an N-channel transistor 125 to turn it off, with the result that the signal line 133 is held at the precharged potential PREC. Therefore, the potential of the signal line 131 becomes lower than that of the signal line 133, so that the potential of the carry signal Cout becomes lower than that of the carry signal /Cout. As a result, a carry is generated to the succeeding stage bit.
On the other hand, when both data are at the logical [0] level, a carry is not generated to the succeeding stage bit, irrespective of the carry signals Cin and /Cin applied by the lower significant bit. In this case, the EX-OR circuit 116 (to which two input data A and B are applied) outputs a logical [0] level signal to the gates of the N-channel transistors 127 and 129, so that these transistors are both turned off. As a result, the carry signals Cin and /Cin are both not transmitted to the succeeding stage bit.
The EX-OR circuit 116 (to which the input data A and B are applied) outputs the logical [0] level signal. The NAND circuit 117 (to which the input data A and B are applied in the same way) outputs the logical [1] level signal. This signal is inverted to the logical [0] level signal by an inverter 119. These two logical [0] level signals of the circuits 116 and 117 and the logical [0] level signal of the precharge signal PREC are all inputted to the NAND circuit 121, so that the NAND circuit 121 outputs the logical [1] level signal. This signal is given to the gate of the N-channel transistor 125 to turn it on, with the result that the signal line 133 is discharged to a low potential Vss. In contrast with this, the NAND circuit 120 outputs a logical [0] level signal. This signal is given to the gate of the N-channel transistor 123 to turn it off, with the result that the signal line 133 is held at the precharged potential PREC. Therefore, the potential of the signal line 131 becomes higher than that of the signal line 133, so that the potential of the carry signal Cout becomes higher than that of the carry signal /Cout. As a result, a carry is not generated to the succeeding stage bit.
When the input data A and B are at the logical [0] level and [1] level, respectively or at the logical [1] level and [0] level, respectively, the carry signals Cin and /Cin applied by the less significant bit decide whether a carry must be generated or not to the succeeding stage bit. When the input data A and B are inputted to the EX-OR circuit 116, the logical [1] level signal is inputted to the gates of the N-channel transistors 127 and 129 to turn them on, respectively. Further, the logical [0] level signal is outputted from the two NAND circuits 120 and 121 to turn off both the N-channel transistors 123 and 125, respectively. As a result, the carry signals Cin and /Cin from the preceding stage bit are outputted, as they are, to the succeeding stage bit as the carry signals Cout and /Cout.
Further, the bits are added as follows: the output result of the EX-OR circuit 116 for inputting input data A and B and the amplified result of the preceding stage carry signal Cin and /Cin by a sense amplifier 113 are both inputted to an EX-OR circuit 118, and the logical operation result thereof is outputted to the outside as an addition data signal SUM OUT.
In the circuit shown in FIG. 1, the carry signals Cin and /Cin inputted from the preceding stage bit are minute-level differential signals and therefore the potential difference between the two is small. After having been amplified by the sense amplifier 113, a differential signal between the two signals Cin and /Cin are inputted to the EX-OR circuit 118 together with the input data A and B. In other words, the addition result can be obtained on the basis of the differential signal with a large amplitude amplified by the sense amplifier 113, without use of the minute-amplitude differential carry signals Cin and /Cin. Accordingly, there exists such a problem in that it takes time to charge and discharge the signal amplified by the sense amplifier, so that the operational speed decreases and simultaneously the current consumption increases.
In addition, the addition data signal SUM OUT outputted by EX-OR circuit 118 must be latched by a latch circuit (not shown) connected to an output terminal of the EX-OR circuit 118. Since this latch circuit is provided separately from the sense amplifier 113, another signal for deciding the latch timing is additionally required, thus causing another problem in that the number of the elements inevitably increases.